1. Technical Field
This disclosure relates to a metal-insulator-metal (MIM) capacitor and a method for manufacturing the same. More particularly, the invention relates to a MIM capacitor including at least one protection layer to provide a stable structure and improved electrical characteristics, and a method for manufacturing the same.
2. Discussion of the Related Art
Known semiconductor memory devices like a dynamic random access memory (DRAM), store information like data or program commands, read the stored information and store other information. A single memory device may have one transistor and one capacitor. For example, a 16 mega-byte DRAM is a highly integrated memory device having 16 million transistors and 16 million capacitors on one chip. The capacitor in the DRAM device may include a storage node, a cell plate and an interlayer insulation layer. The capacitance of a memory device having a capacitor may be improved by enhancing a static capacitance of the capacitor.
As the DRAM device has been highly integrated to over a giga-grade, an area allowed per a unit cell has been decreased so that the static capacitance of not less than about 25 μF/cell, which is necessary for operating the semiconductor device, needs to be ensured from a capacitor having an extremely small area. When a DRAM device is integrated to several mega-grades, a low permittivity material, like silicon oxide (SiO2), silicon oxide/silicon nitride (SiO2/Si3N4), etc., is used to form a thin film dielectric for the capacitor, and doped polysilicon is used as an electrode of the capacitor. Permittivity is also referred to as the dielectric constant (εr) of a material. Polysilicon can be formed into a thin film in a stable process, and easily etched to form desired shapes. When the electrode of the capacitor is formed of the polysilicon, an area (A) of the capacitor may be increased and large capacitance (C) may be ensured.
Capacitors with flat structures have been replaced with box shaped or cylindrical shaped capacitors to ensure the static capacitance of the capacitor. Capacitors including hemisphere particles having increased effective surface area by forming bumps on a surface of the electrode are also known. The capacitor in which silicon is used as an upper electrode and a lower electrode is called a silicon-insulator-silicon (SIS) capacitor.
As the DRAM device has been integrated to giga-grade, it has been difficult to ensure enough capacitance by varying shapes of the capacitor. Accordingly, research has been conducted on a method of using high permittivity dielectrics as the thin film dielectric of the capacitor. While tantalum oxide (Ta2O5) has been researched as a high permittivity dielectric, for example, aluminum oxide (Al2O3), and hafnium oxide (HfO2) have been recently discovered. Generally, silicon oxide (SiO2) has a permittivity of about 3.9, and silicon oxide/silicon nitride (SiO2/Si3N4) has a permittivity of about 7. The above two-component high permittivity dielectrics (Ta2O5, Al2O3, and HfO2) have a permittivity of about 10 to 25.
In order to exhibit properties of the high permittivity material in the capacitor, it is necessary to prevent formation of a low permittivity material on an interface of the upper electrode and the lower electrode. Silicon, a conventional material for the electrodes, is easily oxidized to form an interfacial oxide film at the temperature for depositing the high permittivity material, which leads to difficulty in securing the capacitance of the capacitor. Therefore, a noble metal such as platinum (Pt), ruthenium (Ru), etc. or a heat-resistant metal such as copper (Cu), tungsten (W), tungsten nitride (WN), titanium nitride (TiN), etc is recommended to form the electrodes of the capacitor. On the other hand, with the electrodes including the noble metal or the heat-resistant metal, it is difficult to increase the surface area of the electrodes, and, although the metals have excellent dielectric characteristics, their use is limited. The heat-resistant metal electrodes have poor oxidation characteristics that further limits use of the heat-resistant metal electrodes. A MIM capacitor may have upper and lower electrodes, which are made of the noble metal or the heat-resistant metal.
Aluminum (Al) or aluminum alloy has been used as a material for a connection line of the semiconductor device. Also, research has been performed in connection with manufacturing a semiconductor device including a metal wiring and a MIM capacitor using copper, which has a lower specific resistance than aluminum. The semiconductor device using copper as a contact or as the lower electrode can be manufactured using a damascene process.
FIG. 1A to FIG. 1D are cross-sectional views illustrating a known method for manufacturing a semiconductor device including a MIM capacitor.
Referring to FIG. 1A, an insulation layer 15 is formed of oxide on a semiconductor substrate 10, and portions of the insulation layer 15 are etched using a photolithography process to form an opening (not shown) in the insulation layer 15.
A first metal layer (not shown) is formed of copper on the insulation layer 15 and fills the opening. The first metal layer is polished using a chemical mechanical polishing (CMP) process to form a first metal layer pattern 20 in the opening. The first metal layer pattern 20 serves as the lower electrode of the MIM capacitor.
Referring to FIG. 1B, an upper portion of the first metal layer pattern 20 is etched using a reactive ion etching (RIE) process or a wet etching process. A conductive oxidation protection layer pattern 25 is formed on the first metal layer pattern 20 to complete the lower electrode of the MIM capacitor.
A dielectric layer 30, a second metal layer 35 and an etch stop layer 40 are sequentially formed on the lower electrode of the MIM capacitor and the insulation layer 15. A first photoresist layer (not shown) is coated on the etch stop layer 40, and the first photoresist layer is patterned using a photolithography process to form a first photoresist pattern 45 on the etch stop layer 40.
Referring to FIG. 1C, the etch stop layer 40 and the second metal layer 35 are sequentially etched using the first photoresist pattern 45 as an etch mask to form an upper electrode 50 of the MIM capacitor, and an etch stop layer pattern 55 on the upper electrode 50. The first photoresist pattern 45 is then removed, thereby forming the MIM capacitor.
An interlayer insulation layer (ILD) 60 is formed on the resulting structure including the MIM capacitor. A second photoresist layer (not shown) is coated on the interlayer insulation layer 60. The second photoresist layer is patterned using a photolithography process to form a second photoresist pattern 65 on the interlayer insulation layer 60.
Referring to FIG. 1D, the interlayer insulation layer 60 and the etch stop layer pattern 55 are partially etched using the second photoresist pattern 65 as an etch mask to form via holes (not shown) in the interlayer insulation layer 60, exposing the conductive oxidation protection layer pattern 25 and the upper electrode 50 of the MIM capacitor.
The second photoresist pattern 65 is removed, and the second metal layer (not shown) is formed of tungsten on the interlayer insulation layer 60 and fills the via holes. The second metal layer is polished using a chemical mechanical polishing process to form via contacts 70 in the via holes to connect the MIM capacitor to metal wiring.
In known methods for manufacturing the semiconductor device including the MIM capacitor, when the etch stop layer pattern and the upper electrode are formed using the photoresist pattern as the etch mask, the dielectric layer positioned under the upper electrode is partially removed, which can result in a failure of the capacitor. Additionally, when the etch stop layer pattern and the upper electrode are formed using known methods, the sidewalls of the upper electrode are exposed and subject to damage that can result in the generation of a leakage current. Further, when each structure of the MIM capacitor is formed by an etching process, the structures may be partially damaged during the etching process, resulting in an unstable MIM capacitor structure.